1. Field of the Invention
At least one example embodiment of the present inventive concepts relates to a semiconductor device having a tri-gate transistor and a method of manufacturing the same. According to at least one example embodiment of the present inventive concepts, the semiconductor device may comprise a substrate, a NMOS transistor including a first fin active region protruding from the substrate, and a PMOS transistor including a second fin active region protruding from the substrate. The NMOS transistor and the PMOS transistor may comprise a first metal gate electrode and a second metal gate electrode formed on the first metal gate electrode, respectively.
2. Description of the Related Art
According to high integration of semiconductor devices, a typical transistor has been steadily reduced in size and the transistor's performance, e.g., current-drive performance, also has been degraded. In order to increase the transistor's current-drive performance, there is increasing demand for using a dual-gate transistor having a two-dimensional channel surface or a tri-gate transistor having a three-dimensional channel surface.
As compared with the dual-gate transistor, the tri-gate transistor having a fin-type active region which has an upper surface and a sidewall is structurally more beneficial to improve current-drive performance. However, the tri-gate transistor typically presents some problems. One of the problems is that electric field formed by a gate electrode may be highly concentrated at the intersection of the sidewall and the upper surface of the fin-type active region, therefore the threshold voltage of the tri-gate transistor may be higher due to self-heating phenomenon at the intersection, and the reliability of a gate dielectric layer, e.g., time dependent dielectric breakdown (TDDB), may also be degraded. Therefore, research activities have been focused on reducing the electric field concentration phenomenon at the intersection of the fin-type active region in the tri-gate transistor.